Providing for greater packaging densities, additional functionality and optimized use of limited footprints in microprocessor, integrated circuit and memory design (collectively “chip design”) is highly desired in the electronics and communications industries today. By integrating improved silicon-based chip works into popular devices such as cell phones and computers, the physical size of such devices can be reduced while the functionality of the devices may be increased, with improved performance and efficiency due to the improved chipsets.
Objectives for semiconductor package structures include continued attempts to find opportunities and designs for miniaturization, thereby improving the functional and physical density of components that are packaged in a semiconductor or integrated circuit (i.e., chip or IC). Often designers may seek to find optimized arrangement and placement of components and circuitry encouraging miniaturization while maintain reliability.
For instance, in the practice of reuse of existing maskwork designs, it is desirable to provide sufficient power to drive larger geometries on the processor board for new designs which would logically be provided by the I/O cells. Those I/O cells then would likely still be physically large in comparison to the physical characteristics of on-die logic and therefore would require additional costs for chips requiring a greater number of I/O cells, in part as their footprint may also require more size.
FIG. 1 sets forth a traditional chip layout 100 in which there is a physical footprint of the shape of the substrate platform 105 which includes space for circuits and electronics including core logic 110, physical layer (PHY) logic 120 and input/output (I/O) cells 130. Typically, connections from the core logic 110 to the PHY logic 120 are low speed connections 180 and connections from the PHY logic 120 to the I/O cells 130 are high speed connections 190.
From FIG. 1, connections from the core logic to the PHY logic may be generally symmetric in layout; whereafter connections from PHY logic to I/O cells are approximately similar. In such a design however, the I/O cells require a large footprint of valuable physical layout and similarly the connections between the core logic, PHY logic and I/O cells are also footprint intensive. It is desirable to have a better utilization of the available footprint and improve density usage for performance-based operations.
By example, to effect an implementation improving the density of a chip of a typical wireless handset while limiting the footprint requirement, the base-band processors, memory components and interface bus necessitate a dense level of I/O and wiring. Similarly, it may also be possible to further integrate the memory bus and other functions into the stack for the phone. Many cell phone manufacturers today seek to provide a package platform in which the memory components are stacked or dual onto the processor, often in an attempt to improve both the efficiency and density of limited processor footprint. Similarly, other device manufacturers, such as those involved with personal data assistants (“FDA's”), camcorders, entertainment equipment and devices, notebook computers, etc. (i.e., devices), seek similar objectives.
In practice, by folding or situating the I/O cell on top of one another, a dual row of IO cells may be created on the processor thereby reducing space concerns regarding the highly competitive space constraints of the platform while only minimally increasing the lesser-restrictive height aspects of the platform. FIG. 2 sets forth an example of a dual I/O cell arrangement on a chip 200 in which there is a physical footprint of the shape of the substrate of the platform 205, which includes space for circuits, electronics and core logic 210, PHY logic 220, and dual I/O cells 230. From the Figure, I/O cells are atop other I/O cells at 230 and are preferably edge-aligned. In this arrangement, the PHY logic 220 is typically of lesser dimension in width than the I/O cells. Also, in this arrangement, connections from the core logic 210 to the PHY logic 220 are low speed connections 280 and connections from the PHY logic 220 to the I/O cells 230 are high speed connections 290.
The approach set forth in FIG. 2 provides for a higher density device with a dual row and even quad row configurations being possible. From FIG. 2, while the I/O cells require a smaller footprint, the dimensional issue of the PHY logic (width for instance in comparison to the I/O cells) can become a restrictive factor in design. Comparative with FIG. 1, the chip arrangement of FIG. 2 provides for a more compact design.
However, though the dual row style chip may improve the physical footprint available for other electronic and circuit placement on the processor, the dual I/O cells of FIG. 2 also presents added complexities and limitations in implementation. Inconsistent connection distances between the logic and I/O become apparent and similarly as between the bus and the I/O. These inconsistencies yield potential issues of signal loss or delay as between communication flows from I/O or bus to logic over the inconsistent connection lengths. Unfortunately, the high speed connections as between the PHY logic and the I/O cells, are directly affected in performance where connection lengths are dissimilar. Accordingly, it is important for high speed connection that these connection lengths be as uniform as possible. Further, there remains an ever-increasing need for an approach which is economical and improves efficiencies over existing efforts.
What is desired is an approach that provides for a direct and consistent connection of the stacked I/O with the logic and bus connections of the processor to provide predetermined connection distances consistent with one another for improved performance, with improved economics and reliability and an optimized footprint layout.
As used herein the terms device, apparatus, system, etc. are intended to be inclusive, interchangeable, and/or synonymous with one another and other similar arrangements and equipment for purposes of the present invention though one will recognize that functionally each may have unique characteristics, functions and/or operations which may be specific to its individual capabilities and/or deployment.